Questions
2 questions per end-semester exam
Difficulty
Medium
Importance
High yield for University Architecture exams
Overview
I/O Organization and Pipelining are fundamental concepts in Computer Architecture that dictate how a processor manages external data transfer and optimizes instruction execution. Mastering these topics is essential for university exams, as they form the bridge between theoretical CPU design and practical system performance.
I/O Techniques: Polling and Interrupts
These methods define how the CPU communicates with peripheral devices. While polling keeps the CPU busy checking device status continuously, interrupts allow the CPU to perform other tasks until the device signals it is ready.
- Polling is CPU intensive and leads to waste of clock cycles
- Interrupt-driven I/O uses a hardware signal to request CPU attention
- Vectored interrupts use an interrupt vector table for faster service
- Priority interrupts manage multiple devices requesting service simultaneously
Direct Memory Access (DMA)
DMA is a hardware mechanism that allows peripheral components to transfer data directly to or from main memory without constant CPU involvement. It is the preferred method for high-speed data transfer scenarios like disk I/O.
- DMA controller acts as a proxy processor for data transfer
- Burst Mode transfers large blocks of data in one session
- Cycle Stealing allows DMA to use the bus during CPU idle cycles
- Bus Request (BR) and Bus Grant (BG) are critical handshake signals
Pipelining Basics
Pipelining is a technique where multiple instructions are overlapped in execution, similar to an assembly line in a factory. It improves throughput by allowing different stages of instructions to execute simultaneously.
- Instruction cycle is divided into Fetch, Decode, Execute, Write-back
- Speedup = (Number of stages * N) / (N + k - 1) for N instructions
- Throughput increases as the number of stages increases
- Ideal throughput is one instruction per clock cycle
Pipeline Hazards
Hazards are situations that prevent the next instruction from executing in the subsequent clock cycle. Understanding how to classify and mitigate these is a staple of university-level exam questions.
- Structural Hazards: Hardware resource conflicts
- Data Hazards: Dependency on results of previous instructions
- Control Hazards: Occur due to branch instructions and jumps
- Techniques to resolve: Forwarding, Stall insertion, Branch prediction
Formula Sheet
Speedup = (k * n) / (n + k - 1)
Non-pipelined time = n * k * tp
Pipelined time = (k + n - 1) * tp
Exam Tip
Always draw a labeled pipeline timing diagram when answering questions on hazards, as it accounts for nearly 40% of the total marks in structured theory questions.
Common Mistakes
- Confusing Cycle Stealing with Burst mode in DMA operations
- Failing to draw the space-time diagram for pipeline speedup calculations
- Neglecting the performance penalty of branch misprediction in control hazards
More Revision Notes
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